The present invention relates to a phase locked loops generally and, more particularly, to a memory based phase locked loop.
Phase Locked Loops (PLLs) generally comprise the functional blocks of a delay locked loop and an edge corrector/Voltage Controlled Oscillator (VCO). Conventional approaches are to design these components around specialized analog circuits and counters/dividers using digital logic. The important parameters to control are the duty cycle and jitter on the final clock output across process, power supply and temperature variations.
The present invention concerns a circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.
The objects, features and advantages of the present invention include providing a phase locked loop that may (i) adjust the frequency of oscillation of the PLL with memory cell(s) that may be xe2x80x9ctrimmedxe2x80x9d with separate memory columns during a test phase, (ii) not require a xe2x80x9cwarm-upxe2x80x9d time to establish locking, (iii) be implemented with a variety of memory cell architectures and/or (iv) implement a wide frequency selector range.